1. Field of the Invention
This invention relates to multithreaded processors and, more particularly, to thread selection in a multithreaded processor.
2. Description of the Related Art
Computer processor designs have been improved in a number of ways. Microarchitectures have evolved from single execution unit machines to superscalar designs having multiple pipelines and multiple execution units. To accommodate changing processing environments such as server based applications, for example, a more recent processor design trend includes multithreaded processors capable of executing multiple threads concurrently.
One aspect of multithreading involves thread selection. A thread may have various instruction dependencies that may cause it to stall in the pipeline, while another thread may be able to execute. While the instructions corresponding to the threads are waiting to be selected, they may be stored in an instruction buffer. In general, the design of an instruction buffer may determine its power consumption. Additionally, some buffer structures may require multiplexing which may incur an unacceptable delay due to loading.